In recent years, communication devices such as mobile-phone terminals have made progress in the integration scale of baseband processors, and there has been a trend for such communication devices to have no digital-to-analog converter (DAC) nor analog-to-digital converter (ADC) inside baseband processors for achievement of higher integration according to the scaling down and reduction in power consumption. With this being the case, an interface between a baseband processor and an RFIC (Radio Frequency Integrated Circuit) is arranged to be digital compliant, and a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) are included in an RFIC with a lower packing density rather than a baseband processor.
Further, as seen for communication devices compliant with LTE (Long Term Evolution), the data rate of transmit/receive baseband signals is being increased, and therefore digital interfaces are becoming faster. To cope with such faster digital interfaces, CMOS miniaturization is going on with RFICs. Such CMOS miniaturization leads to larger variations between devices, and the number of circuit blocks on which calibration of property variation inside an RFIC must be conducted is increasing. As a result, a calibration time which can be assigned to each circuit block inside an RFIC tends to be subject to a restriction.
Communication devices including mobile-phone terminals are relatively larger in transmit output power. Therefore, to keep communication devices from interfering with received signals of other users, communication devices are strictly restricted by the standards in spurious levels of receive bands and transmit bands used for other radio systems. For this purpose, with regard to an RFIC with a built-in transceiver, it is essential to lower the noise level in a receive band. In some cases, a filter including a SAW (Surface Acoustic Wave) device is placed between an RFIC and a high power amplifier (HPA) for transmission. However, such an arrangement increases the cost of a mobile-phone terminal. Therefore, there is a tendency to avoid the use of an expensive filter of this type whenever possible.
Polar Modulation systems have been known as an architecture for actualizing a transmitter with reduced noise. Particularly, in the case that a transmitter needs to cope with both GSM (Global System for Mobile Communications), and EDGE (Enhanced Data for GSM. Evolution) systems, a Polar Modulation system, which can materialize a low-noise phase-signal path, has an advantage over other systems including a direct conversion system because GSM is a frequency modulation system. Now, a Polar Modulation system is a system such that I and Q signals in an orthogonal coordinate system are converted into amplitude and phase components, and after up-conversion of the phase signal to a higher frequency, the amplitude and phase components are synthesized, which is as described in the non-patent document presented by Alex W. Hietala, “A Quad-Band 8PSK/GMSK Polar Transceiver”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, No. 5, MAY 2006, PP. 1133-1141.
Five architectures for EDGE-compliant transmitters are shown in the non-patent document presented by Tirdad Sowlati et al., “Quad-Band GSM/GPRS/EDGE Polar Loop Transmitter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, No. 12, DECEMBER 2004, PP. 2179-2189. Of these architectures, the latter three are relevant to a Polar Modulation system. More specifically, two of the three architectures are based on polar modulation means, and the last one is based on polar loop means. These architectures will be described below.
The first architecture of a Polar Modulation system involves the steps of: performing up-conversion of a phase component by use of a PLL (Phase-Locked Loop); and synthesizing amplitude and phase components in a mixer (Mixer) located before a power amplifier, which is herein abbreviated as PA. This arrangement can offer an architecture versatile in use because a typical linear power amplifier can be used. However, since the non-patent document presented by Tirdad Sowlati et al. describes a case that full modulation is performed before the power amplifier, the first architecture is unreliable in terms of its efficiency and output power control.
The second architecture of a Polar Modulation system involves the steps of: performing up-conversion of a phase component by use of a phase-locked loop (PLL); directly modulating an output power of a power amplifier (PA) by an amplitude component; and synthesizing the amplitude and phase components. According to the second architecture, an output of an RFIC can be put in a saturated state. Therefore, the signal-to-noise ratio (S/N) can be improved. Further, the power efficiency of the power amplifier can be increased because the power amplifier can operate remaining saturated. However, in the case of the second architecture, it is necessary to control the power amplifier with large variations in gain, and linearity of output power of the power amplifier is required.
The third architecture of a Polar Modulation system is similar to the second architecture, and it involves the step of synthesizing amplitude and phase components by use of the power amplifier. However, a transmitter according to the third architecture has a feedback path. Like the second architecture, the third architecture can improve the signal-to-noise ratio of an output of an RFIC, and can increase the power efficiency of the power amplifier. In addition, the influence of the non-linearity of the power amplifier, which becomes a problem in the case of the second architecture, can be reduced because a feedback loop is formed.
On another note, International Patent Publication No. JP-T-2008-514044 describes that a delay tracking circuit and a delay circuit are used for compensating the delay mismatch between amplitude and phase components recombined in a power amplifier, which can worsen the adjacent channel leakage power ratio (ACPR) of a polar modulation transmitter. According to JP-T-2008-514044, the delay tracking circuit tracks a delay of the amplitude-signal path, and the delay circuit regulates the phase-signal delay according to the delay of the amplitude-signal path, whereby the delay mismatch is compensated.
Further, Japanese Unexamined Patent Publication No. JP-A-2005-287011 discloses that a polar modulation transmitter is used to conduct a synchronous adjustment for correcting the delay difference between amplitude and phase signals, which can worsen the adjacent channel leakage power ratio (ACPR) and the error vector magnitude (EVM). According to JP-A-2005-287011, amplitude and phase signals for synchronous adjustment are supplied to a delay-difference detector, and the synchronous-adjustment control circuit controls a delay produced by the synchronous adjustment circuit, according to an output of the delay-difference detector.
In addition, Japanese Unexamined Patent Publication No. JP-A-2006-311489 describes means for reducing the variation of the loop gain of a phase-locked loop (PLL) of a radio transmitter for mobile communication. Specifically, an output of the voltage-controlled oscillator (VCO) is supplied to the first input terminal of the phase comparator (PD) of the PLL through a down-conversion mixer (DCM), whereas the frequency of an input signal supplied to the second input terminal of the phase comparator is changed stair-step-wise, and the response to the change is detected by an output of the voltage-controlled oscillator (VCO). In other words, the output of the voltage-controlled oscillator (VCO) is connected with a counter, the output of the counter is connected with an integrator, and the output of the integrator is connected with a control unit. The control unit optimizes the charge-pump current of a charge pump (CP) connected between the phase comparator (PD) and voltage-controlled oscillator (VCO), whereby the loop gain of the PLL is optimized.